Column for SMT magazine - January, 1999 issue

What Can We Expect in 1999? - Part II
by
Dr. Jennie S. Hwang

This is a three-part series: Last month, the column previewed the market demands and notable semiconductor developments. This issue will focus on IC packaging and board-level assembly.

IC Packaging Has the IC packaging technology been keeping pace with silicon technology? Across the two decades 1980s and 1990s, the industry has evolved from DIP (dual-in-line) package, PGA (pin grid array) to 0.050" surface mount LCCC (leadless ceramic chip carrier), PLCC (plastic lead chip carrier), to fine pitch SOIC (small outline IC) and QFP. More recently, BGA, chip scale packages (CSP) and Direct Chip Attach (DCA) have been the focal point. Nonetheless, the 0.020 inch pitch QFP and SOIC continue to be the mainstream of 1999.

After about seventeen years of double-digit growth, surface mount devices will continue enjoying a healthy growth rate at the expense of through-hole components. It is expected that through-hole components will stand a share at less than 15% of the total component units. Among surface mount devices and surface mountable bare dies, the standard surface mount packages, i.e. the combination of SOIC, QFP and PLCC, constitutes more than 70% share. Albeit array packages will have an impressive growth rate, BGA and CSP will fall between 5-10% of total 65-75 billion units of IC packages.

Array packages are primarily driven by high I/O count, board area saving, and the high radio frequency required for wireless communication products. However, the requirement of high density PCB routing and the limited availability of package substrate materials have prevented the growth of high I/O BGA to its fullest potential. The majority of BGAs have been for low I/O applications. The I/O pitch of BGAs generally falls in the range of 1.00 mm - 1.50 mm (0.040 - 0.060 inch). For high I/O count as required in workstations and minicomputers, PBGA, TBGA and CBGA all have been adopted by chip makers. Considering all factors in performance, economics and reliability, I/O count of 250 is considered a break point in selecting between QFP and BGA. While the cost of BGA has been dropping, the cost of QFP reached below $0.008 per I/O.

For products, where the size and weight are critical to their marketability, chip scale package has been the center of attention in 1998, and this will continue in 1999. All six main CSP technologies: wire bond/rigid interposer; wire bond/flex interposer, flip chip/rigid interposer, flip chip/flex interposer, lead-frame/chip on lead, and wafer-level packaging have been put in use.

The relative size of CSPs in comparison with other SMT packages can be well represented by the package area/die area ratio. CSP is generally accepted as less than 1.5 as opposed to BGA (1.25 mm pitch) @ 4, BGA (1.00 mm pitch) @ 2, and QFP (0.4mm pitch @ 7, QFP (0.5 mm pitch) @ 9.0. CSPs have made today's smaller portable electronics possible. For example, Sony's camcorder uses a circuit card that is composed of 18 CSPs supplied by three manufacturers - TI, NEC, and Sony. All three suppliers have designed the CSP with different technologies involving wire bonding/flex (TI), flip chip/TAB (NEC) and, flip chip/rigid PCB (Sony). Matsushita has demonstrated the use of ceramic CSP in mobile phones. In addition to portable consumer electronics, notebook computer is another application that pulls the use of chip scale package for relatively higher I/O ASIC chips. CSPs have also been utilized in flash memory chips and extends to DRAM and SRAM packaging.

While a few specific CSP designs, among the crowd, have emerged as "winners", the proliferation of new designs continues. For example, Sharp Corporation introduced the stacked chip size package to produce ever more compact ICs by stacking two different types of chips in one package. Reportedly, the package reduces the space on PCB to one-third of two TSOPs and to one-half of two CSPs. Sharp and Mitsubishi Electric Corporations agreed to adopt uniform specifications for the stacked CSP, initially intending to unify CSP standards for IC designed for cellular phones and personal handyphone system. A high volume production is planned. Two companies will have combined monthly output to 2 million packages.

Flip Chip Technologies also announced its ultra CSP utilizing wafer-level bumping process. The bump diameter ranges from 0.30 mm (0.012 inch) to 0.50 mm (0.020 inch) with corresponding bump pitch 0.50 mm (0.020 inch) to 0.80 mm (0.031 inch). It is reported that ultra CSP can readily fit to SMT assembly line without the need of underfill. Another wafer-level CSP is demonstrated by Shellcase, Ltd. The thin die in the Shellpack is sandwiched between two glass plates. For applications where the height is most critical such as smart cards, solder bump height becomes an issue. Preference goes to low profile package format.

Another sizzling area is solder bumping development. For last year's projection, this column listed the potential solder bumping processes and stated: "The election of the most efficient solder bumping process will be crystallized." There are two levels of solder bumping - chip/wafer level and substrate level - to be considered. Solder bumping by means of solder paste has gained increased acceptance on the production floor due to its manufacturability and cost advantage. Future challenges are driven by the increase in solder bump density and the decrease in bump size.

Among the three basic on-chip interconnection technologies - wire bonding, flip chip, and TAB, flip chip and wire bonding will continue to co-exist. Flip chip enjoys its superiority in signal-to-noise ratio and data-transfer-rate while wire bonding provides low cost and flexibility in commodating die shrink.

The use of flip chip can be considered in three types - flip chip in BGA, flip chip in CSP, flip chip on main (mother) board without intermediate package. The units of flip chip in both CSP and BGA format will grow in a handsome pace. Flip chip on main board in Direct Chip Attach Format is expected to remain application-specific, such as the success of flip chip in wristwatch application. For cellular phones, choices are among flip chip, CSP, and TSOP with flip chip as an ideal fit.

Overall, portable electronics will pull the development and implementation of CSP and flip chip. Nonetheless, the readiness to fit in existing SMT manufacturing lines as well as the competitive cost will still play a pivotal role to the selection of IC packages.

Board-level assembly
On-going effort will be made on maximizing yield and minimizing defect rate with improved performance properties by utilizing the knowledge and state-of-art equipment and materials that have evolved. Constant assessment of new IC packages in conjunction with board design will become a part of board assembly business. Solder paste will remain the primary interconnection material characterized by its fitness to automated manufacturing, established infrastructures and its metallic nature. Solder paste will not only work for SMT interconnections but also for certain through-hole components (paste-in-hole). Other solder deposition techniques including solder jetting will be assessed for specific packaging and assembly operations. Automation, SMT fitness (e.g. pick-place) and cost will be the determining factors for the viability and vitality of a new technology.

With the introduction of new packages and the increased number of packages types for the PCB assembly, manufacturing process, reflow profile, in particular, warrants further attention. Reflow profile not only affects the production defects and therefore the yield but also the overall reliability of the assembly. A slower heating rate (<2oC/sec, ideally <1oC/sec in preheating zone) in conjunction with lower peak temperature exposure makes a good reflow profile. The same principle should also apply to rework and repair; using preheating and top/bottom heat source will facilitate the process and minimize any potential damages that may occur during rework. BGA rework process and procedures will be established (See this column - November, 1998). The role of inert atmosphere (N2) soldering with low-N2 consumption reflow ovens will be more prominent.

The accuracy and speed of placement equipment will continue to improve. In addition, the "gentle" placement capability to work with small and fragile CSPs will also be on demand including reliable feeding mechanism and vision capability. To handle CSPs in 0.50 mm (0.020 inch) pitch, the position accuracy of ± 0.002 inch is required. Printing and dispensing equipment for the application of solder paste, underfill, adhesives and coatings will be characterized with increased automation and precision. New functional features added to the equipment to facilitate production operation and to enhance the end results continue to emerge. Furthermore environmentally-friendly production operations will become more integrated into future manufacturing. These include CFC-free, reduced VOC processes, lead-free solders and minimal waste and waste-recycling operation.

The initiation of major Japanese corporations to begin to use lead-free solders in home products has come as a surprise. Prompted by Japan's "Home Electronics Recycle Law", companies, namely, Hitachi, Toshiba, Matsushita have implemented lead-free solder in circuit board assembly. Novtel and IEC Electronics also reported the incorporation of lead-free solder in their product. It is expected that lead-free solder will become a renewed endeavor in 1999.

Overall, flexible process, agile manufacturing, and infrastructures equipped with hardware that offers versatile process capabilities are critical to the future success of SMT manufacturing.

(The third part in February will conclude with an overview of complementary technologies including bare board, industry supporting factors, and business climate.)

Column for SMT magazine - February 1999 issue

What More Can We Expect in 1999?
by
Dr. Jennie S. Hwang

Part 3 of a 3-part column series

Last two months, this column looked at overall market demands, notable semiconductor developments, IC packaging, and board-level assembly. This last part of a 3-part column series concludes with bare board and some selected industry and business factors.

Bare board Overall 1999 PCB market is projected at $29.7 billion for rigid board and $2.8 billion for flexible board (per IPC). This constitutes about 10% growth over 1998. The flexible board is still a little shy of 10% of the total.

New alternatives to PCB HASL (hot air solder level) surface finishes have found their way and are more ready than 1998. These include Au/Ni, Pd/Ni, Pd, Ag, Sn, and OSP systems (their comparison will be included in a future column). Electroless Ni and immersion Pd become the practical PCB surface coating systems. Electroless Ni has also made stride into UBM (under-bump-metallurgy) applications.

High density and low cost PCB continues to be the watchword for 1999. Surface build-up and microvia technology will be the focus of efforts. Microvia development on all three techniques - plasma etching, laser drilling, photovia processing, and their improvements are among the major tasks for establishing future PCB fabrication process.

Along with the ability to achieve smaller vias and finer lines, associated processes in PCB fabrication for the betterment of quality, economy and environment will be other active areas. The interdependency between microvias and the use of high I/O flip chip and CSP has been increasingly recognized. Without the sound high-density board technology, high I/O flip chip and CSP can not be fully utilized.

Fundamentally, substrate materials for high frequency (low dielectric constant approaching 2.0), with high glass transition temperature and low moisture absorption are always in demand. Other desirable performance properties include board design and materials that provide efficient thermal management and dimensional stability and low thermal expansion.

In order to fully take advantage of array packages and flip chips, better PCB warpage control becomes mandatory for use as chip substrate for IC packages as well as main boards.

Supporting factors
For coming years, business infrastructure will continue to shift, slowly but steadily. One example, the make-up of in-house dedicated resource and the outsourcing contracted functions will change. As corporations examine the business strategies and assess the global market, outsourcing (as a generic term) will be regarded as one of the viable tactics to maintain competitiveness on the global landscape. For our industry, this translates into the sustained growth of the contract-manufacturing sector. This also extends from SMT board assembly to IC packaging, wafer fabrication, and other specific material and process tasks.

A successful business must possess all three resources - people capital, physical capital, and intellectual capital. The adequate supply of people resource in relevant disciplines is one issue that our industry will be facing in 1999. In general, tighter labor-pool in high-tech area is expected, albeit the issue of engineer shortage is still under debate. Companies are inevitably required to provide more training to the existing workers and to the new employees.

Collaboration between business entities will become essential to the advancement of scientifically-challenging technologies and to the timely introduction of new products.

Y2K
Looking forward to 1999, we can not conclude without a few words about the Y2K issue- -computers that have not been 'fixed" will confuse the year 2000 with the year 1900. Due to the old BIOS chips and software code programmed with only two digits 00 to represent the year, old computers are incapable of automatically going from 1999 to 2000. Actually, the "old' may be as new as 1997.

When the clock strikes at midnight of December 31, 1999, all computer systems will be put in a real test. To many, this will cause more nervousness than to Cinderella. Many operations or transactions may need to be able to distinguish 1900 and 2000 before the year 2000 comes, such as advance orders.

Attention has been drawn to Y2K problem for the recent 2-3 years, although it has largely intensified this year. Tackling the problem thoroughly can be an expensive endeavor. Reportedly, worldwide cost may exceed $300 billion, constituting a significant portion of IT total budget to many operations. This spending however will add about 0.1% to GDP in 1999 (roughly $8 billion) and reduce GDP by 0.3% in 2000 according to economists' analysis (The Wall Street Journal, November 23, 1998).

Some have attributed the use of two-digit representation of the year to limitation and high cost of memory chips in the past. However, this is hardly a convincing justification. Candidly, two practices have been felt as unnatural and uncomfortable all along by this author: (1) using two-digit for the year, '78 instead of 1978; (2) skip 0 in front of the decimal point .84 instead of 0.84 (hopefully this is not construed as hindsight, since it is not). Both practices have been found more prevalent in the U. S. than other countries.

After so much time spent and cost incurred, I have just noticed the recently renewed credit cards are still tenaciously printed the expiration Date - 12/01. Is it really that difficult to print additional two digits - 12/2001?